Nonvolatile semiconductor memory device of virtual-ground memory array with reliable data reading

ABSTRACT

A nonvolatile semiconductor memory device includes a virtual-ground memory array which includes a plurality of word lines and a plurality of bit lines, a row decoder which selectively activates one of the word lines, a column decoder which applies a sense potential to one of the bit lines, and couples all the remaining ones of the bit lines to a ground potential, and a sense amplifier which compares an electric current running through the one of the bit lines with a first reference current and a second reference current so as to sense a data state of two memory cells that are connected to the one of the word lines and share the one of the bit lines, the sensed data state including a first state in which both of the two memory cells are “0”, a second state in which both of the two memory cells are “1”, and a third state in which one of the two memory cells is “1” and another of the two memory cells is “0”.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is based upon and claims the benefit ofpriority from prior Japanese Patent Application No. 2002-140077 filed onMay 15, 2002, with the Japanese Patent Office, the entire contents ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to nonvolatilesemiconductor memory devices, and particularly relates to a nonvolatilesemiconductor memory device having a virtual-ground memory array.

[0004] 2. Description of the Related Art

[0005] In the virtual-ground memory array, bit lines are formed ofdiffusion layers. Among the diffusion layers corresponding to a pair ofbit lines, the one that is coupled to the ground potential functions asa source, and the other that is coupled to the power supply potentialserves as a drain. In such a virtual-ground memory array, the bit-linediffusion layers of a memory cell are shared by adjacent memory cellsthat are situated alongside in the direction of word-line extension.Because of this, the drain contact that is normally provided for eachmemory cell in the NOR-type memory cell array is not necessary, therebyachieving size reduction of memory cells.

[0006]FIG. 1 is a circuit diagram showing a portion of a virtual-groundmemory array.

[0007] The virtual-ground memory array of FIG. 1 includes memory cellsM00 through M23, bit lines BL0 through BL4, and word lines WL0 throughWL2. When data is to be read from the memory cell M02, the word line WL0is set to a predetermined potential to select all the memory cellsconnected to the word line WL. Further, the bit lines BL0 through BL2are set to a drain potential of 1V, for example, and the bit lines BL3and BL4 are coupled to the ground potential. With these settings, thebit line BL2 serves as a drain, and the bit line BL3 functions as asource with respect to the memory cell M02. As shown in FIG. 1, anelectric current Im02 flowing through the memory cell M02 is equal to anelectric current Ibl2 running through the bit line BL2. The data of thememory cell M02 is detected by sensing the electric current Ibl2 by useof a sense amplifier (not shown).

[0008] In such read operation, the reason why the bit line BL1 is set to1V to equalize the bit lines BL1 and BL2 is that there is a need toprevent a leak current from running from the bit line BL2 to the bitline BL1 through the memory cell M01. Under the presence of such a leakcurrent, the electric current Im02 running through the memory cell M02would be different from the electric current Ibl2 flowing through thebit line BL2, so that the detection of the current Ibl2 may not resultin the correct data of the memory cell being obtained.

[0009] In the configuration that prevents a leak current as describedabove, the potential that is applied to the adjacent bit line BL1 isreferred to as a precharge potential, and the potential that is appliedto the read bit line BL2 is referred to as a sense potential.

[0010] Since the bit lines of a virtual-ground memory array are formedof impurity diffusion layers, the resistance of the bit lines isrelatively large, compared to the NOR-type nonvolatile memories in whichbit lines are provided as hardwires formed of a low-resistance metal. Apotential drop is thus likely to occur along the bit lines. As a result,the sense potential and the precharge potential may not be set to thesame voltage as desired.

[0011] A typical construction is such that the sense potential and theprecharge potential are supplied from separate circuits, which mayresult in the supply timing being different between the sense potentialand the precharge potential. In such a case, the sense potential and theprecharge potential may not exhibit the same voltage level.

[0012] When the data of the memory cell M02 shown in FIG. 1 is to bedetected, almost no leak current flows through the memory cell M01 ifthe threshold potential of the adjacent memory cell M01 is high due tothe data status of “0” of the memory cell M01. This is the case evenwhen there is a difference between the precharge potential and the sensepotential. If the threshold potential of the memory cell M01 is low dueto the data status of “1” thereof, however, a difference between theprecharge potential and the sense potential will affect the readoperation.

[0013] Further, it is possible that the threshold of a memory cell maybe erroneously sensed due to the effect of a leak current duringprogram-verify operations or erase-verify operations. In such a case,the reliability of verify operations may suffer greatly. This results inthe threshold potential of data “0” and data “1” having increasedvariation between different memory cells, which reduces a margin forthreshold fluctuation caused by a thermally induced stress or the like.As a result, the reliability of the nonvolatile memory is lowered.

[0014] Accordingly, there is a need for a nonvolatile semiconductormemory device which allows data to be correctly sensed even if a leakcurrent exists in the virtual-ground memory array.

SUMMARY OF THE INVENTION

[0015] It is a general object of the present invention to provide anonvolatile semiconductor memory device that substantially obviates oneor more problems caused by the limitations and disadvantages of therelated art.

[0016] Features and advantages of the present invention will bepresented in the description which follows, and in part will becomeapparent from the description and the accompanying drawings, or may belearned by practice of the invention according to the teachings providedin the description. Objects as well as other features and advantages ofthe present invention will be realized and attained by a nonvolatilesemiconductor memory device particularly pointed out in thespecification in such full, clear, concise, and exact terms as to enablea person having ordinary skill in the art to practice the invention.

[0017] To achieve these and other advantages in accordance with thepurpose of the invention, the invention provides a nonvolatilesemiconductor memory device, including a virtual-ground memory arraywhich includes a plurality of word lines and a plurality of bit lines, arow decoder which selectively activates one of the word lines, a columndecoder which applies a sense potential to one of the bit lines, andcouples all the remaining ones of the bit lines to a ground potential,and a sense amplifier which compares an electric current running throughthe one of the bit lines with a first reference current and a secondreference current so as to sense a data state of two memory cells thatare connected to the one of the word lines and share the one of the bitlines, the sensed data state including a first state in which both ofthe two memory cells are “0”, a second state in which both of the twomemory cells are “1”, and a third state in which one of the two memorycells is “1” and another of the two memory cells is “0”.

[0018] In the nonvolatile semiconductor memory device as describedabove, a memory cell that acts as a current leaking path in theconventional art is included as an object of data sensing, so that thetwo memory cells sharing the sensed bit line are both treated as objectsof data sensing. The electric current flowing through this bit line iscompared with the two different reference currents, thereby sensing thelump-sum data state of the two memory cells. Since all the bit linesother than the sensed bit line are coupled to the ground potential atthe time of data sensing, a precharge operation of bit lines that arenecessary in the conventional art is no longer required. Further, theground potential is extremely stable in comparison with the prechargepotential, and is not susceptible to a potential drop caused by bit-lineresistance. Accordingly, the present invention can completely eliminateerroneous reading of data that occurs in the conventional art due to anunstable potential difference between the sensed bit line and theprecharged bit lines.

[0019] Other objects and further features of the present invention willbe apparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a circuit diagram showing a portion of a virtual-groundmemory array;

[0021]FIG. 2 is a block diagram of a nonvolatile semiconductor memorydevice according to the present invention;

[0022]FIG. 3 is an illustrative drawing for explaining a data sensingoperation according to a first embodiment of the present invention;

[0023]FIG. 4 is a flowchart of the data sensing operation according tothe first embodiment;

[0024]FIG. 5 is an illustrative drawing for explaining a data sensingoperation according to a variation of the first embodiment;

[0025]FIGS. 6A through 6C are illustrative drawings for explaining adata sensing method of a second embodiment according to the presentinvention; and

[0026]FIG. 7 is a flowchart of the data sensing operation according tothe second embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following, embodiments of the present invention will bedescribed with reference to the accompanying drawings.

[0028]FIG. 2 is a block diagram of a nonvolatile semiconductor memorydevice according to the present invention.

[0029] A nonvolatile semiconductor memory device 10 of FIG. 2 includes acontrol circuit 11, a chip-enable-&-output-enable circuit 12, aninput-and-output buffer 13, a cell array 14, a row decoder 15, a columndecoder 16, an address latch 17, a data latch 18, a read circuit 19, awrite circuit 20, an erasure circuit 21, and a reference-currentgenerating circuit 22.

[0030] The control circuit 11 receives address signals, data signals,and control signals such as a write-enable signal /WE and a chip-enablesignal /CE from the exterior, and operates as a state machine based onthese signals, thereby controlling the operation of each unit of thenonvolatile semiconductor memory device 10. The input-and-output buffer13 receives data from the exterior, and supplies the data to the controlcircuit 11 and the data latch 18. The chip-enable-&-output-enablecircuit 12 receives the chip-enable signal /CE and an output-enablesignal /OE as control signals from the exterior of the device, andcontrols the input-and-output buffer 13 and the cell array 14 as towhether they are activated.

[0031] The read circuit 19 operates under the control of the controlcircuit 11, and controls the cell array 14, the row decoder 15, thecolumn decoder 16, etc., through the address latch 17 in order to readdata from the specified address in the cell array 14. The write circuit20 operates under the control of the control circuit 11, and controlsthe cell array 14, the row decoder 15, the column decoder 16, etc.,through the address latch 17 in order to write data at the specifiedaddress in the cell array 14. Moreover, the erasure circuit 21 operatesunder the control of the control circuit 11, and controls the cell array14, the row decoder 15, the column decoder 16, etc., through the addresslatch 17 in order to erase a specified unit area of the cell array 14 atonce by a unit-by-unit basis.

[0032] The cell array 16 is a virtual-ground memory array, and includesan array of memory cell transistors, word lines, bit lines, etc., tostore data in each memory cell transistor. At the time of data-readoperation, data of memory cells selected by an activated word line areretrieved to bit lines. At the time of program operation or eraseoperation, the word lines and the bit lines are set to proper potentialsspecific to the indicated operation, thereby storing or eliminatingelectric charge in the memory cells.

[0033] The data latch 18 operates under the control of the controlcircuit 11, and senses the “0/1” state of data by comparing a datacurrent with a reference current as the data is supplied from the cellarray 14 according to indications by the row decoder 15 and the columndecoder 16. This sensing is carried out by sense amplifier circuits inthe data latch 18, and sense results are supplied to theinput-and-output buffer 13 as retrieved data.

[0034] Moreover, verify operations performed as part of a programoperation or an erase operation are carried out by comparing a datacurrent with a program-verify-purpose reference current or anerase-verify-purpose reference current as the data is supplied from thecell array 14 according to indications by the row decoder 15 and thecolumn decoder 16. The reference-current generating circuit 22 generatesthe reference currents that are used for these data sensing operations.The data latch 18 latches data that is input through theinput-and-output buffer 13 from the exterior during a data writeoperation, and makes the data available for storage in the cell array14.

[0035] In the present invention, the reference-current generatingcircuit 22 generates a first reference current and a second referencecurrent (the second reference current>the first reference current), andthe data latch 18 compares a data current with these two referencecurrents in order to achieve accurate data sensing despite the presenceof a leak current.

[0036]FIG. 3 is an illustrative drawing for explaining a data sensingoperation according to a first embodiment of the present invention.

[0037] The cell array 14 is a virtual-ground memory array, and includesmemory cells M00 through M23, bit liens BL0 through BL4, and word linesWL0 through WL2. The bit lines BL0 through BL4 are connected to thecolumn decoder 16, and the word lines WL0 through WL2 are connected tothe row decoder 15. The column decoder 16 controls the potential of thebit lines BL0 through BL4, and the row decoder 15 controls the potentialof the word lines WL0 through WL2. A sense amplifier 18 a is provided inthe data latch 18 shown in FIG. 2, and carries out a data sensingoperation by comparing a data current with the reference currentssupplied from the reference-current generating circuit 22. Here, thedata current is supplied from the cell array 14 according to indicationsgiven by the row decoder 15 and the column decoder 16.

[0038] When the data of the memory cell M02 is to be read in FIG. 3, theword line WL0 is set to a predetermined voltage (e.g., 2V) so as toselect all the memory cells connected to the word line WL0. Further, thebit line BL2 is coupled to a drain potential such as 1V, with all theother bit lines BL0, BL1, BL3, and BL4 being coupled to the groundpotential. In this case, as shown in FIG. 3, the memory cell M02 and theadjacent memory cell M01 have an electric current Im02 and an electriccurrent Im01 running therethrough, respectively. The current Ibl2 thatflows through the bit line BL2 is a sum of the electric current Im02 andthe electric current Im01.

[0039] The sense amplifier 18 a compares the current Ibl2 with a firstreference current IREF1. A pair of data pieces stored in the pair ofmemory cells M01/M02 is sensed as “0/0” if the current Ibl2 is smallerthan the first reference current IREF1. That is, both of the memorycells M00 and M02 are sensed as the “0” state (i.e., programmed state).

[0040] If the current Ibl2 is larger than the first reference currentIREF1, the sense amplifier 18 a compares the current Ibl2 with a secondreference current IREF2. If the current Ibl2 is larger than the secondreference current IREF2, the data pieces stored in the pair of memorycells M01/M02 are sensed as “1/1”. That is, both of the memory cells M01and M02 are sensed as the “1” state (i.e., erased state). If the currentIbl2 is smaller than the second reference current IREF2, the data piecesstored in the pair of memory cells M01/M02 are sensed as “1/0” or “0/1”.That is, the memory cells M01 and M02 are sensed as having the “1” statein one cell and the “0” state in the other cell.

[0041] In this manner, the current of the bit line to be sensed iscompared with the two types of reference currents, so that a pair ofdata pieces are simultaneously sensed with respect to a pair of memorycells that share this bit line and are adjacent to each other in thedirection of word-line extension. This results in the determination ofeither the “0/0” state, the “1/1” state, or the “1/0 or 0/1” state.

[0042]FIG. 4 is a flowchart of the data sensing operation according tothe first embodiment.

[0043] At a step ST1, a check is made as to whether the current Ibl2 issmaller than the first reference current IREF1. If it is smaller, thepair of memory cells M01/M02 is sensed as “0/0”. Otherwise, theprocedure goes to a step ST2.

[0044] At the step ST2, a check is made as to whether the current Ibl2is larger than the second reference current IREF2. If it is larger, thepair of memory cells M01/M02 is sensed as “1/1”. Otherwise, theprocedure goes to a step ST3.

[0045] At the step ST3, the pair of memory cells M01/M02 are determinedas either “1/0” or “0/1”.

[0046] In the data sensing method according to this embodiment, a datastate of each memory cell can be identified if the data state is either“0/0” or “1/1”. If the data state is the “1/0 or 0/1” sate, however, itcannot be determined as to which one of the two memory cells is “1” andwhich one of the two memory cells is “0”. This data sensing method,nonetheless, makes it possible to effectively check whether all the bitsin the cell array are programmed or all the bits in the cell array areerased.

[0047] If a sense potential is applied to every other bit line BL0, BL2,BL4, and the ground potential is applied to all the other bit lines,data of memory cell pairs can be successively sensed. Since all the bitlines other than the sensed bit line are coupled to the ground potentialat the time of data sensing, a precharge operation of bit lines that arenecessary in conventional operations is no longer required. Further, theground potential is extremely stable in comparison with the prechargepotential, and is not susceptible to a potential drop caused by bit-lineresistance. Accordingly, the present invention can completely eliminateerroneous reading of data that occurs in the conventional operations dueto an unstable potential difference between the sensed bit line and theprecharged bit lines.

[0048] The ability to identify whether data bits are all in the “0”state or all in the “1” state in an efficient and reliable manner isparticularly useful when erasing data of a memory cell array at once bythe unit of one chip or by the unit of one block.

[0049] In the lump erasure of a flash memory, if a memory cell is overlyerased to be in a depletion state, a column leak occurs whereby a leakcurrent flows even when there is no potential difference betweenadjacent bit lines. This results in correct data sensing of memory-celldata being prevented. In order to avoid such over-erasure, all thememory cells to be erased are typically set in the programmed stateprior to the erasure operation. That is, all the memory cells areprogrammed so as to reduce variation of threshold values prior to anerasure operation, so that threshold values of the memory cells afterthe erasure operation also have small variation, which helps to avoidover-erasure. In the flash memories, therefore, all the bits are set tothe “0” state in response to a lump-erasure command, followed by settingthese bits in the “1” state.

[0050] According to the embodiment described above, determination as towhether all the bits are “0” and as to whether all the bits are “1” canbe reliably and quickly made when a lump-erasure command is entered, forexample.

[0051] A nitride film may be employed as a charge capture layer in thevirtual-ground memory array, thereby making it possible to store 2-bitdata in a single memory cell transistor. In such a nonvolatilesemiconductor memory device, two ends of a nitride film situated betweenthe bit lines are treated as two separate memory cells, with 2-bit databeing stored depending on whether hot electrons are injected into therespective cells. This is made possible by utilizing a property thatelectric charge does not move in the charge-capture layer of the nitridefilm.

[0052] In the flash memory of this type, a film composed of an oxidefilm, a nitride film, and an oxide film is formed between the controlgate and the substrate, and electric charge trapped in the nitride filmserves to control the threshold value, thereby discriminating “0” and“1”. In this case, the trap layer made of the nitride film is aninsolating film, so that electric charge does not move. This makes itpossible to store 2-bit data in a single cell by storing electric chargeseparately at the opposite ends of the trap layer. The 2-bit data can beseparately read by swapping the drain and the source over in thedata-read operation.

[0053] Writing to a memory cell is carried out by injecting channel hotelectrons. Potentials of 12V, 8V, and 0V, for example, are applied tothe gate electrode, the drain node, and the source and substrate,respectively, thereby trapping hot electrons in the nitride film as theyare generated in the channel. The hot electrons are injected to aportion of the nitride film close to the drain node. Erasure operationis carried out by hot-hole injection. Potentials of −6V and 5V, forexample, are applied to the gate electrode and the drain node,respectively, thereby injecting holes in the nitride film as they aregenerated by a inter-band tunnel current running from the drain to thesubstrate. These holes neutralize and purge the electric charge. Whenthe electric charge corresponding to two bits are in existence in asingle cell, the same potential as applied to the drain is applied tothe source so as to perform an erasure operation. A read operation iscarried out by a reverse read method that swaps the drain and the sourceover relative to the drain and the source of the write operation.Namely, a diffusion layer that is opposite to the diffusion layer usedas the drain during the write operation is used as a drain in the dataread operation.

[0054] An embodiment that will be described in the following is directedto a flash memory that stores 2-bit data in a single memory cell bystoring electric charge in a trap layer of a nitride film or the like.

[0055]FIG. 5 is an illustrative drawing for explaining a data sensingoperation according to a variation of the first embodiment. In FIG. 5,the same elements as those of FIG. 3 are referred to by the samenumerals, and a description thereof will be omitted.

[0056] A cell array 14A is a virtual-ground memory array that stores2-bit data in a single memory cell, and includes memory cells M00through M23, bit liens BL0 through BL4, and word lines WL0 through WL2.Two boxes are illustrated to represent the positions of two bits inorder to indicate that 2-bit data can be stored in each memory cell.

[0057] When the right-hand-side bit (shown by “x” in the box) of thememory cell M02 and the left-hand-side bit (shown by “x” in the box) ofthe memory cell M01 are to be read, the word line WL0 is set to apredetermined voltage (e.g., 2V). Further, the bit line BL2 is coupledto a drain potential such as 1V, with all the other bit lines BL0, BL1,BL3, and BL4 being coupled to the ground potential. In this case, asshown in FIG. 5, the memory cell M02 and the adjacent memory cell M01have an electric current Im02 and an electric current Im01 runningtherethrough, respectively. The current Ibl2 that flows through the bitline BL2 is a sum of the electric current Im02 and the electric currentIm01.

[0058] The sense amplifier 18 a compares the current Ibl2 with a firstreference current IREF1. A pair of data pieces stored in theM01-left-hand-side bit and the M02-right-hand-side bit is sensed as“0/0” if the current Ibl2 is smaller than the first reference currentIREF1. If the current Ibl2 is larger than the first reference currentIREF1, the sense amplifier 18 a compares the current Ibl2 with a secondreference current IREF2. If the current Ibl2 is larger than the secondreference current IREF2, the data pieces stored in theM01-left-hand-side bit and the M02-right-hand-side bit are sensed as“1/1”. If the current Ibl2 is larger than the first reference currentIREF1 and smaller than the second reference current IREF2, the datapieces stored in the M01-left-hand-side bit and the M02-right-hand-sidebit are sensed as “1/0” or “0/1”.

[0059] The sensing operation described above is the same as that of thefirst embodiment. The way the sense potential is applied for datasensing of each memory cell, however, is different from the firstembodiment. Since each memory cell stores 2-bit data, the sensepotential is successively applied to every one of the bit lines, ratherthan being applied to every other bit line as in the first embodiment.This achieves data sensing with respect to both the right-hand-side bitand the left-hand-side bit of each memory cell.

[0060] In the following, a data sensing method according to a secondembodiment will be described.

[0061] The data sensing method according to the second embodiment isdirected to sensing data stored in each memory cell when data “0” anddata “1” are both present in the floating-gate-type nonvolatile memory(FIG. 3) that stores one-bit data in each memory cell.

[0062]FIGS. 6A through 6C are illustrative drawings for explaining thedata sensing method of the second embodiment according to the presentinvention. FIGS. 6A through 6C show a memory-cell portion that isconnected to the word line WL0, wherein only this portion of the cellarray 14 shown in FIG. 3 is illustrated here for the sake of convenienceof explanation.

[0063] As shown in FIG. 6A, the word line WL0 is set to a predeterminedpotential (e.g., 2V), and the bit line BL0 situated at the end of thememory-cell block is set to a sense potential (e.g., 1V), with all theother bit lines being coupled to the ground potential. Under theseconditions, the electric current Ibl0 flowing through the bit line BL0is compared with the first reference current IREF1. The memory cell M00is identified as being “0” if the current Ibl0 is smaller than the firstreference current IREF1, and is identified as being “1” if the currentIbl0 is larger than the first reference current IREF1.

[0064] The outcome of data sensing of the memory cell M00 is stored ininternal data resisters by the control circuit 11 shown in FIG. 2, forexample, and will be used for subsequent data sensing of the next memorycell M01.

[0065] Following this, as shown in FIG. 6B, the word line WL0 is set toa predetermined potential (e.g., 2V), and the bit line BL1 that is nextto the previously sensed bit line is set to the sense potential (e.g.,1V), with all the other bit lines being coupled to the ground potential.The memory cells M00 and M00 have electric currents Im00 and Im01running through them, respectively. Under these conditions, the electriccurrent Ibl1 flowing through the bit line BL1 is a sum of the currentIm00 and the current Im01.

[0066] If the data of the memory cell M00 that is previously sensed is“0”, the current Ibl1 is compared with the first reference currentIREF1. The memory cell M01 is identified as being “0” if the currentIbl1 is smaller than the first reference current IREF1, and isidentified as being “1” if the current Ibl1 is larger than the firstreference current IREF1.

[0067] If the data of the memory cell M00 that is previously sensed is“1”, the current Ibl1 is compared with the second reference currentIREF2. The memory cell M00 is identified as being “0” if the currentIbl1 is smaller than the second reference current IREF2, and isidentified as being “1” if the current Ibl1 is larger than the secondreference current IREF2.

[0068] The outcome of data sensing of the memory cell M00 is stored ininternal data resisters by the control circuit 11 shown in FIG. 2, forexample, and will be used for subsequent data sensing of the next memorycell M02.

[0069] Following this, as shown in FIG. 6C, the word line WL0 is set toa predetermined potential (e.g., 2V), and the bit line BL2 that is nextto the previously sensed bit line is set to the sense potential (e.g.,1V), with all the other bit lines being coupled to the ground potential.The memory cells M00 and M02 have electric currents Im01 and Im02running through them, respectively. Under these conditions, the electriccurrent Ibl2 flowing through the bit line BL2 is a sum of the currentIm01 and the current Im02.

[0070] After this, the data sensing of the memory cell M02 can becarried out based on the sensed data of the memory cell M01 in the samemanner as the data sensing of the memory cell M01 was carried out basedon the sensed data of the memory cell M00.

[0071]FIG. 7 is a flowchart of the data sensing operation according tothe second embodiment. This flowchart shows a procedure for sensing dataof the memory cell M0n based on the data status of the previously sensedmemory cell M0(n−1).

[0072] At step ST1, a check is made as to whether the preceding memorycell M0(n−1) was “0” or “1”. If it was “0”, an electric current Ibln iscompared with the first reference current IREF1 at step ST2. If thecurrent Ibln is smaller than the first reference current IREF1, thememory cell M0n is sensed as “0” at step ST3. If the current Ibln islarger than the first reference current IREF1, the memory cell M0n issensed as “1” at step ST4.

[0073] If the data of the previously sensed memory cell M0(n−1) was “1”,the electric current Ibln is compared with the second reference currentIREF2 at step ST5. If the current Ibln is smaller than the secondreference current IREF2, the memory cell M0n is sensed as “0” at stepST6. If the current Ibln is larger than the second reference currentIREF2, the memory cell M0n is sensed as “1” at step ST7.

[0074] In this manner, the data status of each memory cell can besuccessively identified by starting from the end of the memory block.This makes it possible to sense the data of each memory cell even when“0” data and “1” data are both present.

[0075] In the following, a description will be given of a case in whichthe present invention is applied to data sensing performed as a writeverify operation or an erase verity operation.

[0076] If it is desired to change a pair of memory cells M01/M02 from“1/1” to “0/1”, the following procedure will be performed.

[0077] The word line WL0 is set to 12V, for example. Then, the bit linesBL0 and BL1 are coupled to the ground potential, and the bit lines BL2,BL3, BL4, . . . are set to 8V. This achieves data writing by injectingelectrons into the floating gate of the memory cell M01 throughhot-electron injection.

[0078] After this, the word line WL0 is set to 1V, and the bit line BL2is set to 1V, with the other bit lines being coupled to the groundpotential. The electric current Ibl2 (=IM01+IM02) that flows through thebit line BL2 is then sensed. In this case, it is already known that thedata of the memory cell M02, i.e., the other cell of the memory cellpair, is “1”, so that it suffices to check whether Ibl2<IREF2. IfIbl2<IREF2, M01/M02 is identified as “0/1”, and the write operation andthe write verify operation come to an end. If the condition “Ibl2<IREF2”is not satisfied, the write operation and the write verify operation asdescribed above will be repeated until the condition “Ibl2<IREF2” issatisfied.

[0079] If it is desired to change the pair of memory cells M01/M02 from“0/1” to “0/0”, the following procedure will be performed.

[0080] The word line WL0 is set to 10V, for example. Then, the bit linesBL0, BL1, and BL2 are coupled to the ground potential, and the bit linesBL3, BL4, . . . are set to 5V. This achieves data writing by injectingelectrons into the floating gate of the memory cell M02 throughhot-electron injection.

[0081] After this, the word line WL0 is set to 1V, and the bit line BL2is set to 1V, with the other bit lines being coupled to the groundpotential. The electric current Ibl2 (=IM01+IM02) that flows through thebit line BL2 is then sensed. In this case, it is already known that thedata of the memory cell M02, i.e., the other cell of the memory cellpair, is “0”, so that it suffices to check whether Ibl2<IREF1. IfIbl2<IREF1, M01/M02 is identified as “0/0”, and the write operation andthe write verify operation come to an end. If the condition “Ibl2<IREF1”is not satisfied, the write operation and the write verify operation asdescribed above will be repeated until the condition “Ibl2<IREF1” issatisfied.

[0082] If it is desired to change the pair of memory cells M01/M02 from“0/0” to “1/1”, the following procedure will be performed.

[0083] The word line WL0 is set to −5V, and the bit line BL2 is set to5V, with all the other bit lines coupled to the ground potential or leftat a floating potential. This achieves data erasure by drainingelectrons from the floating gates of the memory cells M01 and M02 to aBL2 impurity diffusion layer through the FN tunneling method.

[0084] After this, the word line WL0 is set to 1V, and the bit line BL2is set to 1V, with the other bit lines coupled to the ground potential.The electric current Ibl2 (=IM01+IM02) that flows through the bit lineBL2 is then sensed. In this case, both memory cells forming a pair arein the erased state, so that it suffices to check whether Ibl2>IREF2. IfIbl2>IREF2, M01/M02 is identified as “1/1”, and the erase operation andthe erase verify operation come to an end. If the condition “Ibl2>IREF2”is not satisfied, the erase operation and the erase verify operation asdescribed above will be repeated until the condition “Ibl2>IREF2” issatisfied.

[0085] If it is desired to change the pair of memory cells M01/M02 from“0/1” to “1/1”, the following procedure will be performed.

[0086] In this case, pre-programming is necessary in order to avoidover-erasure. A write operation and a write verify operation are thusperformed on the memory cell M02, thereby changing M01/02 from the “0/1”state to the “0/0” state. Thereafter, the erase operation and the eraseverify operation as described above are carried out to change the “0/0”state to the “1/1” state.

[0087] The above embodiment has been described with reference to a casein which the first and second reference currents are constant regardlessof whether it is the read operation, the write verify operation, or theerase verify operation. These reference currents, however, do not haveto be constant. For example, reference currents dedicated for use in thewrite verify operation or dedicated for use in the erase verifyoperation may be provided.

[0088] Further, the present invention is not limited to theseembodiments, but various variations and modifications may be madewithout departing from the scope of the present invention.

What is claimed is
 1. A nonvolatile semiconductor memory device,comprising: a virtual-ground memory array which includes a plurality ofword lines and a plurality of bit lines; a row decoder which selectivelyactivates one of said word lines; a column decoder which applies a sensepotential to one of said bit lines, and couples all the remaining onesof said bit lines to a ground potential; and a sense amplifier whichcompares an electric current running through said one of said bit lineswith a first reference current and a second reference current so as tosense a data state of two memory cells that are connected to said one ofsaid word lines and share said one of said bit lines, the sensed datastate including a first state in which both of the two memory cells are“0”, a second state in which both of the two memory cells are “1”, and athird state in which one of the two memory cells is “1” and another ofthe two memory cells is “0”.
 2. The nonvolatile semiconductor memorydevice as claimed in claim 1, further comprising a control circuit whichcontrols said row decoder, said column decoder, and said senseamplifier.
 3. The nonvolatile semiconductor memory device as claimed inclaim 2, wherein said control circuit identifies a data state of a firstone of the two memory cells based on a known data state of a second oneof the two memory cells if the data state of the two memory cells issaid third state and if a data state of the second one of the two memorycells is known.
 4. A method of sensing data in a nonvolatilesemiconductor memory device, comprising the steps of: selectivelyactivating one of word lines in a virtual-ground memory array whichincludes the word lines and a plurality of bit lines; applying a sensepotential to one of said bit lines and coupling all the remaining onesof said bit lines to a ground potential; comparing an electric currentrunning through said one of said bit lines with a first referencecurrent and a second reference current so as to sense a data state oftwo memory cells that are connected to said one of said word lines andshare said one of said bit lines, the sensed data state including afirst state in which both of the two memory cells are “0”, a secondstate in which both of the two memory cells are “1”, and a third statein which one of the two memory cells is “1” and another of the twomemory cells is “0”.
 5. A method of sensing data in a nonvolatilesemiconductor memory device, comprising the steps of: selectivelyactivating one of word lines in a virtual-ground memory array whichincludes the word lines and a plurality of bit lines; applying a sensepotential to a first bit line in a row of said bit lines and couplingall the remaining ones of said bit lines to a ground potential;comparing an electric current running through said first bit line with afirst reference current; sensing a data state of a first memory cell inresponse to said comparing wherein said first memory cell is a first onein a row of memory cells connected to said one of said word lines and isconnected to said first bit line; comparing an electric current runningthrough an n-th one of said bit lines with a reference current that isselected in response to a data state of a (n−1)-th one of said memorycells, so as to sense a data state of a n-th one of said memory cells,wherein said (n−1)-th one of said memory cells and said n-th one of saidmemory cells share said n-th one of said bit lines.
 6. The method asclaimed in claim 5, wherein the reference current compared with theelectric current running through said n-th one of said bit lines is saidfirst reference current if the data state of said (n−1)-th one of saidmemory cells is “0”, and is a second reference current larger than saidfirst reference current if the data state of said (n−1)-th one of saidmemory cells is “1”.